3D-Partition: A Design Space Exploration Tool for Three-Dimensional Network-on-Chip
نویسنده
چکیده
In this paper, we introduce a compositive model of fabrication cost, network throughput and power consumption, to explore different 3D design options of 3D NoCs. The model allows partition of IPs across different dies in 3D stack. Based on the model an estimation tool, 3D-Partition, is created and validated by comparing its results with those obtained from NIRGAM. Effects of various 3D NoC architectures under different 3D IC partition strategies on cost, throughput and power consumption are explored to demonstrate the utility of the tool. It provides economic and performance reference to designing 3D ICs for volume production in the future. Keywords-3D NoC; design space exploration; many-core processor design.
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